The present invention relates to a semiconductor integrated circuit, and particularly to a technique useful in its application to a semiconductor integrated circuit device having a fine multilayer interconnection.
The structure of the multilayer interconnection generally adopted at present is as follows: A metallic layer, such as an aluminum layer, formed by deposition on an insulating film having contact holes in predetermined positions is etched into a desired pattern to form a first wiring layer. An inter-layer insulating film having a through-hole in a predetermined position is formed on the first wiring layer and the insulating film. A second wiring layer is formed by etching a metallic layer, such as an aluminum layer, formed by deposition on the inter-layer insulating film so as to make contact with the first wiring layer through the through-hole. Further, a second inter-layer insulating film is formed on the second wiring layer. Thereafter, the same construction is repeated to constitute a multilayer interconnection. With higher integration, namely decreasing the size of circuit components, the wiring layer width becomes narrower, resulting in marked disconnection caused by electromigration. To avoid this inconvenience, there has been adopted a technique of enhancing the resistance to electromigration by replacing aluminum as the wiring layer-forming metal with a metal, e.g. tungsten, having a melting point higher than that of aluminum.
As a literature describing tungsten wiring there is mentioned VLSI Multilevel Interconnection. Conf. No. 86CH23374, p. 418 (1986).